This is the second post of 'Lets's do it' series. It talks about question asked in digital circuit design interview.
a reference link for questions - http://www.techinterviews.com/large-list-of-intel-interview-questions
Key difficulty in voltage scaling
- Need to scale voltage for power
- hard since Vth does not scale.
Silicide
- it is a metal - silicon alloy
Power
Ptotal = Pdyn + Pstat
Pdyn = Ptran + Psc ( sc - short circuit)
Ptot = Pdyn + Psc + Pstat
Ptot = CVcc(2)f + VccImax(tr+tf)(1/2)f + VccIleak
Reducing dynamic power
- reduce voltage
- reduce capacitance
- reduce frequency
Reducing short circuit current
- fast rise and fall times on input signals
- - reduce input capacitance
- - insert small buffers to "clean up" slow input signals before sending to large gate
Large output load, doesn't let the output to switch quickly so there is less time for both transistors to be ON at the same time.
High threshold voltage can also help in reducing the short circuit current.
Reducing leakage current
- reduce transistors size
- lower voltage
- increase threshold voltage ( to reduce leakage through gate)
- - high-K dielectric replacing SiO2
- reduce temperature by reducing power by reducing frequency/Area/f/Cap
**Sub-threshold leakage- when transistor is OFF due to Vds, a current flows. It depends on threshold voltage, DIBL. Threshold voltage can be lowered by reducing the Vds or increasing the source voltage or increasing negative potential of bulk. This all reduces the subthreshold leakage.
This leakage increases with temperature because threshold voltage reduces with temperature.
Series transistors leak less because each NMOS will have less Vds across drain and source and thus less DIBL and thus less leakage.( refer to diagram below)
|Vdd
_|
||
||_
|
|Vx
_|
||
||_
|
|gnd
But other factors also come into picture. Raising Vt by controlling DIBL and short channel effects causes BTBT to increase. Applying a reverse body bias to increase Vt also increases BTBT.
Applying a negative gate voltage to turn the transistor OFF more strongly causes GIDL to increase.
** gate leakage - carriers tunnel through thin gate dielectric. strong function of dielectric thickness.
Gate leakage can be alleviated by stacking transistors such that the OFF transistors is closer to the rail.
why always P substrate
- Both P-well and N-well CMOS processes exist.The N-well process offers a slightly better NMOS transistor, and it allows the use of a grounded substrate.
NAND v/s NOR
- NOR occupies more area for same delay and current because it has transistors with double the size of transistors in NAND.
-NAND NOR
2 2 4
2 4
2 1 1
-NAND uses transistors of similar sizes.
-NAND offers less delay
Two input mux using 4 NOR gates (assume inputs are available for negative signals too)
a reference link for questions - http://www.techinterviews.com/large-list-of-intel-interview-questions
Key difficulty in voltage scaling
- Need to scale voltage for power
- hard since Vth does not scale.
Silicide
- it is a metal - silicon alloy
Power
Ptotal = Pdyn + Pstat
Pdyn = Ptran + Psc ( sc - short circuit)
Ptot = Pdyn + Psc + Pstat
Ptot = CVcc(2)f + VccImax(tr+tf)(1/2)f + VccIleak
Reducing dynamic power
- reduce voltage
- reduce capacitance
- reduce frequency
Reducing short circuit current
- fast rise and fall times on input signals
- - reduce input capacitance
- - insert small buffers to "clean up" slow input signals before sending to large gate
Large output load, doesn't let the output to switch quickly so there is less time for both transistors to be ON at the same time.
High threshold voltage can also help in reducing the short circuit current.
Reducing leakage current
- reduce transistors size
- lower voltage
- increase threshold voltage ( to reduce leakage through gate)
- - high-K dielectric replacing SiO2
- reduce temperature by reducing power by reducing frequency/Area/f/Cap
**Sub-threshold leakage- when transistor is OFF due to Vds, a current flows. It depends on threshold voltage, DIBL. Threshold voltage can be lowered by reducing the Vds or increasing the source voltage or increasing negative potential of bulk. This all reduces the subthreshold leakage.
This leakage increases with temperature because threshold voltage reduces with temperature.
Series transistors leak less because each NMOS will have less Vds across drain and source and thus less DIBL and thus less leakage.( refer to diagram below)
|Vdd
_|
||
||_
|
|Vx
_|
||
||_
|
|gnd
But other factors also come into picture. Raising Vt by controlling DIBL and short channel effects causes BTBT to increase. Applying a reverse body bias to increase Vt also increases BTBT.
Applying a negative gate voltage to turn the transistor OFF more strongly causes GIDL to increase.
** gate leakage - carriers tunnel through thin gate dielectric. strong function of dielectric thickness.
Gate leakage can be alleviated by stacking transistors such that the OFF transistors is closer to the rail.
why always P substrate
- Both P-well and N-well CMOS processes exist.The N-well process offers a slightly better NMOS transistor, and it allows the use of a grounded substrate.
NAND v/s NOR
- NOR occupies more area for same delay and current because it has transistors with double the size of transistors in NAND.
-NAND NOR
2 2 4
2 4
2 1 1
-NAND uses transistors of similar sizes.
-NAND offers less delay
Two input mux using 4 NOR gates (assume inputs are available for negative signals too)
No comments:
Post a Comment